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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad538 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 real-time analog computational unit (acu) functional block diagram 25k v 25k v log ratio 100 v 25k v 25k v antilog log output 100 v ad538 internal voltage reference i v o i z v z b +10v Cv s +v s +2v i y a d i x v x c pwr gnd signal gnd v y 118 17 16 15 14 13 12 11 10 2 3 4 5 6 7 8 9 features v out = v y v z v x ? ? ? ? m transfer function wide dynamic range (denominator) C1000:1 simultaneous multiplication and division resistor-programmable powers and roots no external trims required low input offsets <100 m v low error 6 0.25% of reading (100:1 range) +2 v and +10 v on-chip references monolithic construction applications one- or two-quadrant mult/div log ratio computation squaring/square rooting trigonometric function approximations linearization via curve fitting precision agc power functions product description the ad538 is a monolithic real-time computational circuit that provides precision analog multiplication, division and exponen- tiation. the combination of low input and output offset voltages and excellent linearity results in accurate computation over an unusually wide input dynamic range. laser wafer trimming m akes multiplication and division with errors as low as 0.25% of read- ing possible, while typical output offsets of 100 m v or less add to the overall off-the-shelf performance level. real-time analog signal processing is further enhanced by the devices 400 khz bandwidth. the ad538s overall transfer function is v o = v y (v z /v x ) m . programming a particular function is via pin strapping. no external components are required for one-quadrant (positive input) multiplication and division. two-quadrant (bipolar numerator) division is possible with the use of external level shifting and scaling resistors. the desired scale factor for both multiplication and division can be set using the on-chip +2 v or +10 v references, or controlled externally to provide simulta- neous multiplication and division. exponentiation with an m value from 0.2 to 5 can be implemented with the addition of one or two external resistors. direct log ratio computation is possible by using only the log ratio and output sections of the chip. access to the multiple summing junctions adds further to the ad538s flexibility. finally, a wide power supply range of 4.5 v to 18 v allows operation from standard 5 v, 12 v and 15 v supplies. the ad538 is available in two accuracy grades (a and b) over the industrial (C25 c to +85 c) temperature range and one grade (s) over the military (C55 c to +125 c) temperature range. the device is packaged in an 18-lead to-118 hermetic side-brazed ceramic dip. a-grade chips are also available. product highlights 1. real-time analog multiplication, division and exponentiation. 2. high accuracy analog division with a wide input dynamic range. 3. on-chip +2 v or +10 v scaling reference voltages. 4. both voltage and current (summing) input modes. 5. monolithic construction with lower cost and higher reliability than hybrid and modular circuits.
C2C rev. c ad538Cspecifications ad538ad ad538bd ad538sd parameters conditions min typ max min typ max min typ max units multiplier divider performance nominal transfer function 10 v 3 v x , v y , v z 3 0v o = v y v z v x ? ? ? ? m v o = vy v z v x ? ? ? ? m v o = v y v z v x ? ? ? ? m 400 m a 3 i x , i y, i z 3 0v o = 25 k w i y i z i x ? ? ? ? m v o = 25 k w i y i z i x ? ? ? ? m v o = 25 k w i y i z i x ? ? ? ? m total error terms 100 mv v x 10 v 0.5 6 1 0.25 6 0.5 0.5 6 1 % of reading + 100:1 input range 1 100 mv v y 10 v 200 6 500 100 6 250 200 6 500 m v 100 mv v z 10 v v z 10 v x , m = 1.0 t a = t min to t max 1 6 2 0.5 6 1 1.25 6 2.5 % of reading + 450 6 750 350 6 500 750 6 1000 m v wide dynamic range 2 10 mv v x 10 v 1 6 2 0.5 6 1 1 6 2 % of reading + 1 mv v y 10 v 200 6 500 100 6 250 200 6 500 m v + 0 mv v z 10 v 100 6 250 750 6 150 200 6 250 m v (v y + v z )/v x v z 10 v x , m = 1.0 t a = t min to t max 1 6 3 1 6 2 2 6 4 % of reading + 450 6 750 350 6 500 750 6 1000 m v + 450 6 750 350 6 500 750 6 1000 m v (v y + v z )/v x exponent (m) range t a = t min to t max 0.2 5 0.2 5 0.2 5 output characteristics offset voltage v y = 0, v c = C600 mv 200 6 500 100 6 250 200 6 500 m v t a = t min to t max 450 6 750 350 6 500 750 6 1000 m v output voltage swing r l = 2 k w C11 +11 C11 + 11 C11 + 11 v output current 5 10 5 10 5 10 ma frequency response slew rate 1.4 1.4 1.4 v/ m s small signal bandwidth 100 mv 10 v y , v z , 400 400 400 khz v x 10 v voltage reference accuracy v ref = 10 v or 2 v 25 6 50 15 6 25 25 6 50 mv additional error t a = t min or t max 20 6 30 20 6 30 30 6 50 mv output current v ref = 10 v to 2 v 1 2.5 1 2.5 1 2.5 ma power supply rejection +2 v = v ref 4.5 v v s 18 v 300 600 300 600 300 600 m v/v +10 v = v ref 13 v v s 18 v 200 500 200 500 200 500 m v/v power supply rated r l = 2 k w 15 15 15 v operating range 3 6 4.5 6 18 6 4.5 6 18 6 4.5 6 18 v psrr 4.5 v < v s < 18 v 0.5 0.1 0.05 0.1 0.5 0.1 %/v v x = v y = v z = 1 v v out = 1 v quiescent current 4.5 7 4.5 7 4.5 7 ma temperature range rated C25 +85 C25 +85 C55 +125 c storage C65 +150 C65 +150 C65 +150 c package options ceramic (d-18) ad538ad ad538bd ad538sd ad538sd/883b chips ad538achips notes 1 over the 100 mv to 10 v operating range total error is the sum of a percent of reading term and an output offset. with this inp ut dynamic range the input offset contribution to total error is negligible compared to the percent of reading error. thus, it is specified indirectly as a part of the percent of reading error. 2 the most accurate representation of total error with low level inputs is the summation of a percent of reading term, an output offset and an input offset multiplied by the incremental gain (v y + v z ) v x . 3 when using supplies below 13 v, the 10 v reference pin must be connected to the 2 v pin in order for the ad538 to operate correctly. specifications subject to change without notice. specifications shown in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality l evels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. (v s = 6 15 v, t a = +25 8 c unless otherwise noted)
ad538 C3C rev. c re-examination of multiplier/divider accuracy traditionally, the accuracy (actually the errors) of analog multipliers and dividers have been specified in terms of percent of full scale. thus specified, a 1% multiplier error with a 10 v full-scale output would mean a worst case error of +100 mv at any level within its designated output range. while this type of error specification is easy to test evaluate, and interpret, it can leave the user guessing as to how useful the multiplier actually is at low output levels, those approaching the specified error limit (in this case) 100 mv. the ad538s error sources do not follow the percent of full- scale approach to specification, thus it more optimally fits the needs of the very wide dynamic range applications for which it is best suited. rather than as a percent of full scale, the ad538s error as a multiplier or divider for a 100:1 (100 mv to 10 v) input range is specified as the sum of two error components: a percent of reading (ideal output) term plus a fixed output offset. following this format the ad538ad, operating as a multiplier or divider with inputs down to 100 mv, has a maximum error of 1% of reading 500 m v. some sample total error calculations for both grades over the 100:1 input range are illustrated in the chart below. this error specification format is a familiar one to designers and users of digital voltmeters where error is specified as a percent of reading a certain number of digits on the meter readout. for operation as a multiplier or divider over a wider dynamic range (>100:1), the ad538 has a more detailed error specifica- tion that is the sum of three components: a percent of reading term, an output offset term and an input offset term for the v y /v x log ratio section. a sample application of this specifica- tion, taken from table i, for the ad538ad with v y = 1 v, v z = 100 mv and v x = 10 mv would yield a maximum error of 2.0% of reading 500 m v (1 v + 100 mv)/10 mv 250 m v or 2.0% of reading 500 m v 27.5 mv. this example illus- trates that with very low level inputs the ad538s incremental gain (v y + v z )/v x has increased to make the input offset contri- bution to error substantial. table i. sample error calculation chart (worst case) v y v z v x ideal total offset % of reading total error total error summation input input input output error term error term summation as a % of the ideal (in v) (in v) (in v) (in v) (in mv) (in mv) (in mv) output 100:1 10 10 10 10 0.5 (ad) 100 (ad) 100.5 (ad) 1.0 (ad) input 0.25 (bd) 50 (bd) 50.25 (bd) 0.5 (bd) range total error = 10 0.1 0.1 10 0.5 (ad) 100 (ad) 100.5 (ad) 1.0 (ad) % rdg 0.25 (bd) 50 (bd) 50.25 (bd) 0.5 (bd) output v os 1 1 1 1 0.5 (ad) 10 (ad) 10.5 (ad) 1.05 (ad) 0.25 (bd) 5 (bd) 5.25 (bd) 0.5 (bd) 0.1 0.1 0.1 0.1 0.5 (ad) 1 (ad) 1.5 (ad) 1.5 (ad) 0.25 (bd) 0.5 (bd) 0.75 (bd) 0.75 (bd) wide 1 0.10 0.01 10 28 (ad) 200 (ad) 228 (ad) 2.28 (ad) dynamic 16.75 (bd) 100 (bd) 116.75 (bd) 1.17 (bd) range total error = 10 0.05 2 0.25 1.76 (ad) 5 (ad) 6.76 (ad) 2.7 (ad) % rdg 1 (bd) 2.5 (bd) 3.5 (bd) 1.4 (bd) output v os input v os 5 0.01 0.01 5 125.75 (ad) 100 (ad) 225.75 (ad) 4.52 (ad) (v y + v z )/v x 75.4 (bd) 50 (bd) 125.4 (bd) 2.51 (bd) 10 0.01 0.1 1 25.53 (ad) 20 (ad) 45.53 (ad) 4.55 (ad) 15.27 (bd) 10 (bd) 25.27 (bd) 2.53 (bd)
ad538 C4C rev. c ordering guide temperature package package model range description option ad538ad C25 c to +85 c side-brazed ceramic dip d-18 ad538bd C25 c to +85 c side-brazed ceramic dip d-18 ad538achips C25 c to +85 c chips ad538sd C55 c to +125 c side-brazed ceramic dip d-18 ad538sd/883b C55 c to +125 c side-brazed ceramic dip d-18 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation . . . . . . . . . . . . . . . . . . . . 250 mw output short circuit-to-ground . . . . . . . . . . . . . . . indefinite input voltages v x , v y , v z . . . . . . . . . . . . . (+v s C 1 v), C1 v input currents i x , i y , i z , i o . . . . . . . . . . . . . . . . . . . . . . 1 ma operating temperature range . . . . . . . . . . . C25 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature, storage . . . . . . . . . . . . . . 60 sec, +300 c thermal resistance q jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 c/w q ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 c/w pin configuration 1 2 18 17 5 6 7 14 13 12 3 4 16 15 8 11 910 i z v z a d +2v +v s Cv s pwr gnd c b +10v i x v o i y iv y signal gnd v x ad538 top view (not to scale) caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad538 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ad538 C5C rev. c total % of reading error temperature C 8 c C55 C40 C20 0 20406080 100 125 5.0 4.0 3.0 2.0 1.0 0 1000 800 600 400 200 0 offset % of reading output stage offset C m v figure 1. multiplier error vs. temperature (100 mv < v x , v y , v z 10 v) temperature C 8 c total % of reading error output stage offset C m v C55 C40 C20 0 20406080 100 125 5.0 4.0 3.0 2.0 1.0 0 1000 800 600 400 200 0 offset % of reading figure 2. divider error vs. temperature (100 mv < v x , v y , v z 10 v) input fre q uency C hz 1000 100 100 10 1 1k 10k 100k 1m v x = 10v v y = 0v v z = 5v +5v sin v t volts v o in mv peak-to-peak figure 3. v z feedthrough vs. frequency typical performance characteristicsC denominator voltage, v x C v dc 1m 0.01 100k 10k 0.1 1 10 400k 40k v y = 10v dc v z = v x +0.05 v x sin v t small signal bandwith C hz figure 4. small signal bandwidth vs. denominator voltage (one-quadrant mult/div) total % of reading error output stage offset C m v temperature C 8 c C55 C40 C20 0 20406080 100 125 5.0 4.0 3.0 2.0 1.0 0 1000 800 600 400 200 0 6.0 % of reading offset 1200 figure 5. multiplier error vs. temperature (10 mv < v x , v y , v z 100 mv) temperature C 8 c C55 C40 C20 020406080 100 125 5.0 4.0 3.0 2.0 1.0 0 1000 800 600 400 200 0 % of reading offset total % of reading error output stage offset C m v figure 6. divider error vs. temperature (10 mv < v x , v y , v z 100 mv)
ad538 C6C rev. c 25k v 25k v log ratio 100 v 25k v 25k v antilog log output 100 v ad538 internal voltage reference i v o i z v z b +10v Cv s +v s +2v i y a d i x v x c pwr gnd signal gnd v y 118 17 16 15 14 13 12 11 10 2 3 4 5 6 7 8 9 figure 9. functional block diagram functional description as shown in figures 9 and 10, the v z and v x inputs connect directly to the ad538s input log ratio amplifiers. this subsec- tion provides an output voltage proportional to the natural log of input voltage v z , minus the natural log of input voltage v x . the output of the log ratio subsection at b can be expressed by the transfer function: v b = kt q ln v z v x ? ? ? ? where k = 1.3806 10 C23 j/k, q = 1.60219 10 C19 c, t is in kelvins. the log ratio configuration may be used alone, if correctly tem- perature compensated and scaled to the desired output level (see applications section). under normal operation, the log-ratio output will be directly connected to a second functional block at input c, the antilog subsection. this section performs the antilog according to the transfer function: v o = v y e v c q kt ? ? ? ? as with the log-ratio circuit included in the ad538, the user may use the antilog subsection by itself. when both subsections are combined, the output at b is tied to c, the transfer function of the ad538 computational unit is: v o = v y e kt q ? ? ? ? q kt ? ? ? ? ln v z v x ? ? ? ? ? ? ; v b = v c which reduces to: vv v v oy z x = ? ? ? ? finally, by increasing the gain, or attenuating the output of the log ratio subsection via resistor programming, it is possible to raise the quantity v z /v x to the m th power. without external programming, m is unity. thus the overall ad538 transfer function equals: v o = v y v z v x ? ? ? ? m where 0.2 < m < 5. when the ad538 is used as an analog divider, the v y input can be used to multiply the ratio v z /v x by a convenient scale factor. the actual multiplication by the v y input signal is accomplished by adding the log of the v y input signal to the signal at c, which is already in the log domain. input frequency C hz 150 100 10 1.0 0.1 1k 10k 100k 1m 100 v x = 10v v y = 5v +5v sin v t volts v z = 0v v o in mv peak-to-peak figure 7. v y feedthrough vs. frequency dc output voltage C volts 100 0.01 voltage noise, e n C m v hz 10 1 0.10 0.01 0.1 1 10 for the frequency range of 10hz to 100khz the total rms output noise, e o , for a given bandwidth bw, is calculated e o = e n bw v x = 10v v x = 0.01v figure 8. 1 khz output noise spectral density vs. dc output voltage
ad538 C7C rev. c stability precautions at higher frequencies, the multistaged signal path of the ad538, as illustrated in figure 10, can result in large phase shifts. if a condition of high incremental gain exists along that path (e.g., v o = v y v z /v x = 10 v 10 mv/10 mv = 10 v so that d v o / d v x = 1000), then small amounts of capacitive feedback from v o to the current inputs i z or i x can result in instability. appro priate care should be exercised in board layout to pre- vent ca pacitive feedback mechanisms under these conditions. log e i y v y ln y log e i z v z ln z log e i x v x ln x 0.2 # m # 5 buffer + ++ C ln z C ln x m(ln z C ln x) m(ln z C ln x) +ln y v o = v y v z v x m antilog e ss figure 10. model circuit using the voltage references a stable bandgap voltage reference for scaling is included in the ad538. it is laser-trimmed to provide a selectable voltage out- put of +10 v buffered (pin 4), +2 v unbuffered (pin 5) or any voltages between +2 v and +10.2 v buffered as shown in figure 11. the output impedance at pin 5 is approximately 5 k w . note that any loading of this pin will produce an error in the +10 v reference voltage. external loads on the +2 v output should be greater than 500 k w to maintain errors less than 1%. 25k v 25k v log ratio 100 v 25k v 25k v antilog log output 100 v ad538 internal voltage reference i v o i z v z b ref out Cv s +v s +2v i y a d i x v x c pwr gnd signal gnd v y 118 17 16 15 14 13 12 11 10 2 3 4 5 6 7 8 9 50k v 11.5k v +2v to +10.2v buffered figure 11. +2 v to +10.2 v adjustable reference in situations not requiring both reference levels, the +2 v output can be converted to a buffered output by tying pins 4 and 5 together. if both references are required simultaneously, the +10 v output should be used directly and the +2 v output should be externally buffered. one-quadrant multiplication/division figure 12 shows how the ad538 may be easily configured as a precision one-quadrant multiplier/divider. the transfer function v out = v y (v z /v x ) allows three independent input variables, a calculation not available with a conventional multiplier. in addition, the 1000:1 (i.e., 10 mv to 10 v) input dynamic range of the ad538 greatly exceeds that of analog multipliers comput- ing one-quadrant multiplication and division. 25k v 25k v log ratio 100 v 25k v 25k v antilog log output 100 v ad538 internal voltage reference i v o i z v z b +10v +2v i y a d i x v x c pwr gnd signal gnd v y 1 18 17 16 15 14 13 12 11 10 2 3 4 5 6 7 8 9 v z input +15v C15v output v x input v y input in4148 v out = v y ( ) v z v x figure 12. one-quadrant combination multiplier/divider by simply connecting the input v x (pin 15) to the +10 v refer- ence (pin 4), and tying the log-ratio output at b to the antilog input at c, the ad538 can be configured as a one-quadrant analog multiplier with 10-volt scaling. if 2-volt scaling is desired, v x can be tied to the +2 v reference. when the input v x is tied to the +10 v reference terminal, the multiplier transfer function becomes: v o = v y v z 10 v ? ? ? ? as a multiplier, this circuit provides a typical bandwidth of 400 khz with values of v x , v y or v z varying over a 100:1 range (i.e., 100 mv to 10 v). the maximum error with a 100 mv to 10 v range for the two input variables will typically be +0.5% of reading. using the optional z offset trim scheme, as shown in figure 13, this error can be reduced to +0.25% of reading. by using the +10 v reference as the v y input, the circuit of figure 12 is configured as a one-quadrant divider with a fixed scale factor. as with the one-quadrant multiplier, the inputs accept only single (positive) polarity signals. the output of the one-quadrant divider with a +10 v scale factor is: v o = 10 v v z v x ? ? ? ? the typical bandwidth of this circuit is 370 khz with 1 v to 10 v denominator input levels. at lower amplitudes, the band- width gradually decreases to approximately 200 khz at the 2 mv input level.
ad538 C8C rev. c log ratio operation figure 14 shows the ad538 configured for computing the log of the ratio of two input voltages (or currents). the output signal from b is connected to the summing junction of the output ampli- fier via two series resistors. the 90.9 w metal film resistor effec- tively de grades the temperature coefficient of the 3500 ppm/ c resistor to produce a 1.09 k w +3300 ppm/ c equivalent value. in this configuration, the v y input must be tied to some voltage less than zero (C1.2 v in this case) removing this input from the transfer function. the 5 k w potentiometer controls the circuits scale factor ad- justment providing a +1 v per decade adjustment. the output offset potentiometer should be set to provide a zero output with v x = v z = 1 v. the input v z adjustment should be set for an output of 3 v with v z = l mv and v x = 1 v. 25k v 25k v log ratio 100 v 25k v 25k v antilog log output 100 v ad538 internal voltage reference 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 i v o i z v z b +10v +2v i y a d i x v x c pwr gnd signal gnd v y +15v C15v in4148 v o = 1v log 10 ( ) v z v x output 2k v 1% 5k v scale factor adjust ad589 C1.2v Cv s optional input v os adjustment v x input 1m v 10m v 90.9 v 1% 1k v +3500 ppm/ 8 c +v s Cv s 10m v 10k v optional output v os adjustment 68k v 5% 48.7 v figure 14. log ratio circuit the log ratio circuit shown achieves 0.5% accuracy in the log domain for input voltages within three decades of input range: 10 mv to 10 v. this error is not defined as a percent of full- scale output, but as a percent of input. for example, using a 1 v/decade scale factor, a 1% error in the positive direction at the input of the log ratio amplifier translates into a 4.3 mv deviation from the ideal output (i.e., 1 v log 10 (1.01) = 4.3214 mv). an input error 1% in the negative direction is slightly different, giving an output deviation of 4.3648 mv. two-quadrant division the two-quadrant linear divider circuit illustrated in figure 13 uses the same basic connections as the one-quadrant version. however, in this circuit the numerator has been offset in the positive direction by adding the denominator input voltage to it. the offsetting scheme changes the dividers transfer function from: v o = 10 v v z v x ? ? ? ? to: v o = 10 v v z + av x () v x = 10 v 1 a + v z v x ? ? ? ? = 10 a + 10 v v z v x ? ? ? ? where a = 35 k w 25 k w ? ? ? ? as long as the magnitude of the denominator input is equal to or greater than the magnitude of the numerator input, the cir- cuit will accept bipolar numerator voltages. however, under the conditions of a 0 v numerator input, the output would incor- rectly equal +14 v. the offset can be removed by connecting the +10 v reference through resistors r1 and r2 to the output sections summing node i at pin 9 thus providing a gain of 1.4 at the center of the trimming potentiometer. the pot r2 adjusts out or corrects this offset, leaving the desired transfer function of 10 v (v z /v x ). 25k v 25k v log ratio 100 v 25k v 25k v antilog log output 100 v ad538 internal voltage reference 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 i v o i z v z b +10v +2v i y a d i x v x c pwr gnd signal gnd v y +15v C15v in4148 v out = 10 ( ) v z v x for v x $ v z output r1 12.4k v r2 10k v zero adjust ad589 1m v v os adj 68k v 5% 3.9m v 35k v numerator v z 10m v C1.2v Cv s optional z offset trim denominator v x 35k v figure 13. two-quadrant division with 10 v scaling
ad538 C9C rev. c analog computation of powers and roots it is often necessary to raise the quotient of two input signals to a power or take a root. this could be squaring, cubing, square- rooting or exponentiation to some noninteger power. examples include power series generation. with the ad538, only one or two external resistors are required to set any desired power, over the range of 0.2 to 5. raising the basic quantity v z /v x to a power greater than one requires that the gain of the ad538s log ratio subtractor be increased, via an external resistor between pins a and d. similarly, a voltage divider that attenuates the log ratio output between points b and c will program the power to a value less than one. 3121817 2 10 15 8 v y ( ) m v z v ref r a v o v z v y v ref v x bcad r a = 196 v m C1 r b = r c # 200 v powers m r a 2 196 v 3 97.6 v 4 64.9 v 5 48.7 v 312 2 10 15 8 v y ( ) m v z v ref v o v z v y v ref v x bc r b r c roots m r b r c 1/2 100 v 100 v 1/3 100 v 49.9 v 1/4 150 v 49.9 v 1/5 162 v 40.2 v r b r c = C1 1 m figure 15. basic configurations and transfer functions for the ad538 +15v C15v d1 in4148 v out = 1v v in 1v * * r c 100 v r b 100 v v out 7 1 8 6 4 2 3 +v s in4148 in4148 ad op-07 or ad611 (v os tap to Cv s ) Cv s 20k v 5k v 20k v optional absolute value section 10k v v in +2v 1k v 1k v 100 v scale factor trim ratio match 1% metal film resistors for best accuracy * 25k v 25k v log ratio 100 v 25k v 25k v antilog log output 100 v ad538 internal voltage reference i v o i z v z b +10v i y a d i x v x c pwr gnd signal gnd v y 118 17 16 15 14 13 12 11 10 2 3 4 5 6 7 8 9 +2v v os 20k v figure 16. square root circuit square root operation the explicit square root circuit of figure 16 illustrates a precise method for performing a real-time square root computation. for added flexibility and accuracy, this circuit has a scale factor adjustment. the actual square rooting operation is performed in this circuit by raising the quantity v z /v x to the one-half power via the resistor divider network consisting of resistors r b and r c . for maximum linearity, the two resistors should be 1% (or better) ratio-matched m etal film types. one volt scaling is achieved by dividing-down the 2 v reference and applying approximately 1 v to both the v y and v x inputs. in this circuit, the v x input is intentionally set low, to about 0.95 v, so that the v y input can be adjusted high, permitting a 5% scale factor trim. using this trim scheme, the output volt- age will be within 3 mv 0.2% of the ideal value over a 10 v to 1 mv input range (80 db). for a decreased input dynamic range of 10 mv to 10 v (60 db) the error is even less; here the output will be within 2 mv 0.2% of the ideal value. the bandwidth of the ad538 square root circuit is approximately 280 khz with a 1 v p-p sine wave with a +2 v dc offset. this basic circuit may also be used to compute the cube, fourth or fifth roots of an input waveform. all that is required for a given root is that the correct ratio of resistors, r c and r b , be selected such that their sum is between 150 w and 200 w . the optional absolute value circuit shown preceding the ad538 allows the use of bipolar input voltages. only one op amp is required for the absolute value function because the i z input of the ad538 functions as a summing junction. if it is necessary to preserve the sign of the input voltage, the polarity of the op amp output may be sensed and used after the computation to switch the sign bit of a d.v.m. chip.
ad538 C10C rev. c transducer linearization many electronic transducers used in scientific, commercial or industrial equipment monitor the physical properties of a device and/or its environment. sensing (and perhaps compensating for) changes in pressure, temperature, moisture or other physical phenomenon can be an expensive undertaking, particularly where high accuracy and very low nonlinearity are important. in conventional analog systems accuracy may be easily increased by offset and scale factor trims, however, nonlinearity is usually the absolute limitation of the sensing device. with the ability to easily program a complex analog function, the ad538 can effectively compensate for the nonlinearities of an inexpensive transducer. the ad538 can be connected be- tween the transducer preamplifier output and the next stage of monitoring or transmitting circuitry. the recommended proce- dure for linearizing a particular transducer is first to find the closest function which best approximates the nonlinearity of the device and then, to select the appropriate exponent resistor value(s). arc-tangent approximation the circuit of figure 17 is typical of those ad538 applications where the quantity v z /v x is raised to powers greater than one. in an approximate arc-tangent function, the ad538 will accu- rately compute the angle that is defined by x and y displace- ments represented by input voltages v x and v z . with accuracy to within one degree (for input voltages between 100 m v and 10 volts), the ad538 arc-tangent circuit is more precise than conventional analog circuits and is faster than most digital tech- niques. for a direct arc-tangent computation that requires fewer external components, refer to the ad639 data sheet. the circuit shown is set up for the transfer function: vv v v v ref z x qq q =- () () () ? ? 121 . where: q= tan - 1 z x ? ? ? ? the ( v q ref C v q ) function is implemented in this circuit by adding together the output, v q , and an externally applied refer- ence voltage, v q ref , via an external ad547 op amp. the 1 m f capacitor connected around the ad547s 100 k w feedback resistor frequency compensates the loop (formed by the ampli- fier between v q and v y ). 25k v 25k v log ratio 100 v 25k v 25k v antilog log output 100 v ad538 internal voltage reference v u = [v u ref Cv u ] 3 ( ) u = tan C1 ( ) v z v x z x 1.21 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 i v o i z v z b +10v +2v i y a d i x v x c pwr gnd signal gnd v y Cv s in4148 ratio match 1% metal film resistors for best accuracy * +v s 1 m f 1 m f +15v C15v v u v z ad547jh r2 * 100k v +15v C15v 0.1 m f 100k v 1 m f 118k v r1 * 100k v 10k v full-scale adjust r a 931 v , 1% v x figure 17. the arc-tangent function the v b /v a quantity is calculated in the same manner as in the one-quadrant divider circuit, except that the resulting quotient is raised to the 1.21 power. resistor r a (nominally 931 w ) sets the power or m factor. for the highest arc-tangent accuracy the external resistors r1 and r2 should be ratio matched; however, the offset trim scheme shown in other circuits is not required since nonlinearity effects are the predominant source of error. also note that insta- bility will occur as the output approaches 90 because, by defini- tion, the arc-tangent function is infinite and therefore, the ad538s gain will be extremely high.
ad538 C11C rev. c side-brazed ceramic dip (d-18) 18 1 9 10 0.30 (7.62) 0.28 (7.12) pin 1 seating plane 0.02 (0.508) 0.015 (0.381) 0.17 (4.32) max 0.175 (4.45) 0.125 (3.18) 0.06 (1.53) 0.04 (1.02) 0.91 (23.12) 0.89 (22.61) 0.105 (2.67) 0.095 (2.42) 0.306 (7.78) 0.294 (7.47) 0.012 (0.305) 0.008 (0.203) 0.12 (3.05) 0.06 (1.53) outline dimensions dimensions shown in inches and (mm). printed in u.s.a. c959dC0C12/99 (rev. c)

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